Modern CPUs Need Smarter Scheduling (2025-10-24)
Current and future CPUs offer more than just cores and sockets. HPC schedulers require information about L3, L2 caches, cache groups (like AMD's CCX), and power/efficiency cores to allow scenarios like "run only on power cores" or "pack application inside one core complex" to get the best and most stable performance results.
Gridware Cluster Scheduler 9.1.0 introduces topology-aware scheduling that understands these complex hardware layouts. The scheduler uses a simple notation to represent CPU topology:
| Letter | Meaning |
|---|---|
| N | NUMA node |
| S | Socket |
| X | L3 cache / Chiplet |
| Y | L2 cache group |
| C | Power core |
| E | Efficiency core |
| T | Thread (SMT) |
Example topology string:
NSXCTTCTTCTTCTTEYEEYEE
This represents a socket with power cores (dual-threaded) and efficiency cores (grouped by L2 cache), all sharing an L3 cache—exactly the kind of heterogeneous design found in modern Intel, AMD, and ARM processors.
Check out Ernst Bablick's comprehensive blog post , where the engineer behind this feature explains the implementation with real-world examples from NVIDIA DGX Spark, Intel i9-14900HX, and AMD EPYC Zen5 systems.
Update 1: Please also check the follow up article Compute Nodes with Heterogeneous Topology in Gridware Cluster Scheduler
Update 2: Please also check the second follow up article How Binding Order and Range Shape Job Placement in Gridware Cluster Scheduler